In any integrated circuit, there is an inevitable capacitance that is introduced from electromagnetic interaction between electrical conductors, such as interconnect layers (metals). There are two components of such capacitance, a bulk (area) component and a fringe (peripheral) component. The bulk component is proportional to the overlap area of interconnect layers and the fringe component depends on the separation and the perimeter of adjacent interconnect layers. Referring now to FIG. 1, the bulk capacitance 102 and the fringe capacitance 104 between Metal 1 and Metal 2 of an exemplary integrated circuit 100 are shown. The bulk capacitance generated due to the overlap of signal carrying lines on Metal 1 and Metal 2 may not be easily avoided since the placement of signal carrying lines is dictated by circuit functionality. However, the bulk capacitance introduced due to the overlap of non-signal carry lines may be reduced by changing the placement of non-signal carry lines.
An example of non-signal carry lines includes “dummy” fills which are utilized to even the topography and pattern density across the chip, prevent etch, or the like. “Dummy” fills refer to additional features to an integrated chip layout. In a typical integrated chip layout, there are unused areas on a layer after the signal, power and clock segments have been routed. These unused areas can be large enough such that additional features (metals) should be added to satisfy minimum metal coverage requirements for manufacturing. The “dummy” fills may be added to the unused areas such that subsequent layers on the integrated circuit are substantially planar.
For example, a dummy fills methodology is utilized in chemical mechanical polishing or planarization (CMP) process. Often, the planer profile resulting from the CMP process is dependent on the pattern density of the underlying layer. The density may vary and thus result in CMP planer profile variation. Such CMP planer profile variation may be reduced by employing the dummy fills methodology. In particular, dummy fills (dummy features) are inserted into a wafer prior to the CMP process so as to make the pattern density more uniform in IC chips. Uniform feature density improves wafer-processing uniformity for certain operations such as CMP. Dummy fills are typically placed according to conventional dummy fills methodologies that locate dummy fills where space is available. However, the conventional dummy fills methodologies allow a large planer profile variation. Some sophisticated dummy fills methodologies are utilized to reduce the large planer profile variation by selectively inserting dummy fills to achieve an effective density to within a predetermined range.
While most dummy fills methodologies have focused on uniform feature density, the problems created by the inserted dummy fills such as adverse effects on the electric field, unwanted bulk capacitance, and the like have not been addressed. Further, the existing dummy fill methodologies treat each layer independently which results in a large overlap over dummy fill areas on successive layers. Referring now to FIG. 2, the overlaps 206 between Metal 1 dummy fill area 202 and Metal 2 dummy fill area 204 are shown. If the overlaps 206 are large, the unwanted bulk capacitance may be increased, thereby slowing down signals in the circuit and adversely affecting timing.
Therefore, it would be desirable to provide a method and system of intelligent dummy fill placement to reduce inter-layer capacitance caused by overlaps of dummy fill area on successive layers. It would be also desirable to provide a method and system for treating each consecutive pair of layers together when the intelligent dummy filling placement is performed.